Shanshan Xie

News

1 journal paper accepted to JSSC

1 paper accepted to VLSI 2022

Research Interest

Mixed Signal Integrated Circuit Design, Modeling and Analysis
Compute-in-Memory Techniques
Mixed Signal Approaches for ML Accelerator

Worcester Polytechnic Institute (WPI)

Bachelor of Science (BS)

Major: Electrical & Computer Engineering

GPA 3.97/4.00, May 2018

The University of Texas at Austin

Ph.D. Student

Major: Electrical & Computer Engineering

Expected Graduation: May 2023

Publication

• S. Xie, S. Raman, C. Ni, M. Wang, M. Yang, and J. Kulkarni, “Ising-CIM: A Reconfigurable and Scalable Compute within Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems’ JSSC, 2022
• S. Xie, C. Ni, P. Jain, F. Hamzaoglu, and J. Kulkarni, “Gain-cell CIM: Leakage-Aware 2T1C Gain-Cell eDRAM Based Com-pute in Memory Design Featuring Bitline Precharge DACs, and Compact Schmitt Trigger ADCs,” VLSI, 2022
• Siddhartha Raman Sundara Raman, Shanshan Xie, and Jaydeep P. Kulkarni “Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors” Special session on Analog Computing, SoC, and Processing-in-Memory for AI Hardware, IEEE International Symposium on Circuits & Systems, (ISCAS), May 2021, DOI: 10.1109/ISCAS51556.2021.9401798
• Meizhi Wang, Shanshan Xie, Ping Na Li, Aseem Sayal, Ge Li, Vishnuvardhan V. Iyer, Aditya Thimmaiah, Michael Orshansky, Ali E. Yilmaz, and Jaydeep P. Kulkarni. “Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management” in IEEE Custom Integrated Circuits Conference (CICC), April 2021
• Meizhi Wang, Vishnuvardhan V. Iyer, Shanshan Xie, Ge Li, Sanu K. Mathew, Raghavan Kumar, Michael Orshansky, Ali E. Yilmaz, and Jaydeep P. Kulkarni, “Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks”, in IEEE Custom Integrated Circuits Conference (CICC), April 2021
• S. Xie, C. Ni, A. Sayal, P. Jain, F. Hamzaoglu, J. Kulkarni, “eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded Dynamic Memory Array Realizing Adaptive Data Converters and Charge Domain Computing” IEEE International Solid State Circuits Conference (ISSCC), pp. 248-249, February 2021
• S. Raman, S. Xie and J. Kulkarni, “Compute in Memory Design using Indium Gallium Zinc Oxide Transistor based Monolithic 3-D stacked, Multi-level, embedded DRAM,” IBM IEEE CAS/EDS – AI Compute Symposium
• S. Xie, D. Sen, J. McNeill, Y. Mendelson R. Dunn & K. Hickle “A predictive model for force-sensing resistor nonlinearity for pressure measurement in a wearable wireless sensor patch,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
• D. Sen, J. McNeill, S. Xie, Y. Mendelson R. Dunn & K. Hickle “Time-domain-based measurement technique for pressure measurement in a wearable wireless sensor patch,” International Symposium on Circuits and Systems (ISCAS), 1-5.
• J. Yanamadala, G. Noetscher, M. Piazza, A. Helderman, N. Thang, T. Dolma, T. Trinh, J. Zhang, M. Islam, S. Xie, V. Rathi, S. Maliye, H. Win, A. Tran, X. Jackson, P. Carberry, A. Htet, M. Kozlov, S. Louie, A. Nazarian, S. Makarov “VHP-Female v. 2.0 Full-Body Computational Phantom: ANSYS HFSS Performance Metrics in Application to Antenna Radiation and Scattering,” 39th Antenna Applications Symposium, Monticello, IL, Sep. 22- 24, 2015, pp. 453-461

Awards/Achievements

• Cadence Women in Technology Scholarship (2020)
• 2017 - 2018 Eta Kappa Nu (HKN) Outstanding Senior Tutor, WPI, April 2018
• 2016 – 2017 Eta Kappa Nu (HKN) Outstanding Senior Tutor, WPI, March 2017
• Tau Beta Pi (Engineering Honor Society), WPI, October 2016
• IEEE – Eta Kappa Nu (Electrical and Computer Engineering Honor Society), WPI, October 2016